// $$$ : hit0300_clone_2.v -- lan adaptor HIT-0300 clone (use MB86967).
//
//  used device:
//		XC9572XL-5-VQ44 - G2 bus (simple bus mode) interface
//		MB86967         - lan controller
//		TC55257DFL-70L  - buffer SRAM 32kbytes
//		93C46           - sirial EEPROM (for MAC address)
//
//	device address mapping:
//		0xa0600400 - 0xa060047c: (long word alignment) MB86967 lan controller device
//		0xa0600480: reset port register
//
//									date 2007/11/10  designed by jj1odm

`timescale 1ns / 1ps

module hit0300_clone_2(
    input modemcsn,		// G2 bus modem area enable {simple bus mode} (activ low)
    input lben_wrn,		// G2 bus write strobe {simple bus mode} (active low)
    input uben_rdn,		// G2 bus read strobe {simple bus mode} (activ low)
    inout [7:0] d,		// G2 bus data bus {simple bus mode} (ad[7:0] 8bit data bus)
    input [5:0] a,		// G2 bus address bus {simple bus mode} (ad[15:8] 8bit adr. bus / use 6bit(ad[13:8]))
    input resetn,		// G2 bus system reset (active low)
	output irqan,		// G2 bus interrupt IRQA (active low)

    output csn,			// MB86967 ALE (active low)
    output rdn,			// MB86967 /IOR (active low)
    output wrn,			// MB86967 /IOW (active low)
    inout [7:0] sd,		// MB86967 data bus (8 bit)
    output reset,		// MB86967 chip reset (active high)

	input ireq0			// MB86967 IREQ0 (active high)
);

    parameter RESET_REG = 6'b100000;	// reset port register

    reg [7:0] dreg;			// for g2 bus
    reg reset_reg;			// reset port register

	assign irqan = ~ireq0;	// inverse interrupt signal
    
    assign csn = ~(~modemcsn & (a[5] == 1'b0));	// MB86967 chip select
    assign rdn = ~(~csn & ~uben_rdn);			// MB86967 read strobe
    assign wrn = ~(~csn & ~lben_wrn);			// MB86967 write strobe
    assign reset = ~resetn | reset_reg;			// MB86967 chip reset

    assign sd = (~csn & rdn) ? d : 8'hzz;
    assign d = dreg;
    
    always @(uben_rdn or modemcsn or a or sd or d or reset_reg) begin
   	    if (~modemcsn & ~uben_rdn) begin	// read
            if (a[5] == 1'b0) begin			// read MB86967 registers
                dreg <= sd;
            end
            else begin	// read reset port register
                dreg <= a == RESET_REG ? {7'b0000000, reset_reg} : 8'hzz;
            end
        end
        else dreg <= 8'hzz;
    end
    
    always @(posedge lben_wrn or negedge resetn) begin
    	if (~resetn) begin
    	    reset_reg <= 1'b0;
    	end
    	else begin
	    	if (~modemcsn & a == RESET_REG) reset_reg <= d[0];
	    end
    end
    
endmodule

// end of : hit0300_clone_2.v