About the transplant to the NT system.

1) i/o access

 in al, dx
 out dx, al

 This can be solved with 'giveio.sys'.

2) Disable and enable of interrupt

 cli  // _disable()
 sti  // _enable()

 Interrupt is prohibited at the data transfer of each minimum.
 This problem might have to correspond by the device driver.

------------------- part of ppi.c -------------------------

// byte_out() -- PC -> Dreamcast (1 byte = 2bit x 4)

PUBLIC void byte_out(uchar data)
{
    _disable();
    __asm {
        mov     bh, byte ptr stb_reg
        mov     ah, bh
        and     ah, ~CLOCK
        mov     dx, word ptr ppi_base // dx = PRNDATA
        mov     cl, dl
        add     cl, 2       // cl = PRNDATA + 2
        mov     bl, byte ptr data // bl = data
        rol     bl, 3       // from msb bit

        mov     al, bl      //  al = (bl & 3)
        and     al, 6       //        
        out     dx, al      // data out
        mov     al, ah      // clock on
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //
        rol     bl, 2

        mov     al, bl      //  al = (bl & 3)
        and     al, 6       //        
        out     dx, al      // data out
        mov     al, bh      // clock off
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //
        rol     bl, 2

        mov     al, bl      //  al = (bl & 3)
        and     al, 6       //        
        out     dx, al      // data out
        mov     al, ah      // clock on
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //
        rol     bl, 2

        mov     al, bl      //  al = (bl & 3)
        and     al, 6       //        
        out     dx, al      // data out
        mov     al, bh      // clock off
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //
    }
    _enable();
}

// tri_byte_in() -- PC <- Dreamcast (3 byte = 3bit x 8)

PUBLIC void tri_byte_in(uchar *p)
{
    _disable();
    __asm {
        push    esi
        mov     esi, dword ptr p
        mov     ch, byte ptr stb_reg
        mov     ah, ch
        and     ah, ~CLOCK
        mov     dx, word ptr ppi_base // dx = PRNDATA
        mov     cl, dl
        add     cl, 2       // cl = PRNDATA + 2
        xor     ebx, ebx
    
        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        shl     ebx, 3      // ebx <<= 3
        mov     al, ah      // clock on
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        shl     ebx, 3      // ebx <<= 3
        mov     al, ch      // clock off
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        shl     ebx, 3      // ebx <<= 3
        mov     al, ah      // clock on
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        shl     ebx, 3      // ebx <<= 3
        mov     al, ch      // clock off
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        shl     ebx, 3      // ebx <<= 3
        mov     al, ah      // clock on
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        shl     ebx, 3      // ebx <<= 3
        mov     al, ch      // clock off
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        shl     ebx, 3      // ebx <<= 3
        mov     al, ah      // clock on
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        in      al, dx      // data in
        and     al, 7       // al &= 7
        or      bl, al      // bl |= al
        mov     al, ch      // clock off
        xchg    dl, cl      //
        out     dx, al      //
        xchg    dl, cl      //

        mov     [esi+1], bh
        mov     [esi+2], bl
        ror     ebx, 8
        mov     [esi], bh
        pop     esi
    }
    _enable();
}