// $$$ : bba_clone.v -- Dreamcast BBA clone.
//
//  used circuit: bba_clone.gif
//  used device:
//		fpga: EPF6016AQC-208 (Altera flex6000)
//		ram: KM688257AJ-10 x 2 {16bit data bus}
//		lan controller: RTL8139C (PCI Lan card) {PCI bus connector}
//  last update:
//
//	device map: (physical address)
//	 0x01001400-0x0100140f: "GAPSPCI_BRIDGE_2" strings {read only} (16bytes)
//	 0x01001410-0x01001413: 0x0c003000 ??? {read only} (4bytes}
//	 0x01001418-0x0100141b: magic code register {long access only} (4bytes) {RTL8139C config sequence}
//		write: 0x5a14a501 {config start} / read: bit[31:1] '0', bit[0] - config done bit
//	 0x01001420-0x01001423: register ??? (4bytes) {register only}
//	 0x01001424-0x01001427: register ??? (4bytes) {register only}
//	 0x01001428-0x0100142b: register ??? (4bytes) {register only}
//	 0x0100142c-0x0100142f: register ??? (4bytes) {register only}
//   0x010016xx			  : ???
//   0x01001700-0x010017ff: {PCI} RTL8139C registers (256bytes) {after config}
//	*0x01001800-0x01001803: pci_ad[31:0] {read only} (4bytes) {for debug}
//	*0x01001804-0x01001805: pci_cbe[3:0] {read only} (2bytes) {for debug}
//	*0x01001806-0x01001807: configuration address register (2bytes) {for debug}
//  *0x01001808-0x0100180b: {PCI} configuration data register (4bytes) {for debug}
//   0x01840000-0x01847fff: {PCI} packet buffer (32Kbytes)
//
//                                  date 2007/11/19  designed by jj1odm

`timescale 1ns / 1ps

`define	DMA_BUFFER	13'h0184		// DMA buffer memory base address 0xa1840000 (G2 bus and PCI bus)

module bba_clone(
	// G2 bus
    input g2_clk,		// G2 bus system clock (25MHz)
    input g2_resetn,	// G2 bus system reset
    input g2_aen,		// G2 bus address enable (active low)
    input g2_lben,		// G2 bus direction and lower byte enable (active low) [change name: dir => g2_lben]
    input g2_uben,		// G2 bus upper byte enable (active low) [change name: den => g2_uben]
    inout [15:0] g2_ad,	// G2 bus address/data multiplexed bus (16 bit)
    output g2_btan,		// G2 bus bus termination A (active low)
    output g2_btbn,		// G2 bus bus termination B (active low)
    input g2_etc15,		// G2 bus 15pin
    output g2_irqan,	// G2 bus interrupt A (open drain active low)
    output g2_irqbn,	// G2 bus interrupt B (open drain active low)

	// PCI bus
	inout [31:0] pci_ad,	// PCI address / data bus (32bit)
	inout [3:0] pci_cbe,	// PCI command / byte bit map bus (4bit)
	input pci_reqbn,		// PCI req B {RTL8139C} (active low)
	output pci_gntbn,		// PCI gnt B {RTL8139C} (active low)
	inout pci_framen,		// PCI frame (active low)
	inout pci_irdyn,		// PCI irdy (active low)
	inout pci_trdyn,		// PCI trdy (active low)
	inout pci_devseln,		// PCI devsel (active low)
	output pci_idsel,		// PCI idsel {for RTL8139C} (active high)
	inout pci_stopn,		// PCI stop (active low)
	inout pci_par,			// PCI parity
	inout pci_perrn,		// PCI perr (active low)
	inout pci_serrn,		// PCI serr (active low)

	// fast SRAM bus {KM688257AJ-10 x 2} ((8bit x 32768) x 2)
    output [14:0] sram_a,	// SRAM address bus (15bit)
    inout [15:0] sram_d,	// SRAM data bus (16bit)
    output sram0_csn,		// SRAM 0 chip select {lower byte} (active low)
    output sram1_csn,		// SRAM 1 chip select {upper byte} (active low)
    output sram0_oen,		// SRAM 0 output enable {lower byte} (active low)
    output sram1_oen,		// SRAM 1 output enable {upper byte} (active low)
    output sram0_wen,		// SRAM 0 write enable {lower byte} (active low)
    output sram1_wen,		// SRAM 1 write enable {upper byte} (active low)

	// etc. debug & test signals
	input cfg_a_disn,	// config A disable (active low) {debug: magic code config disabe switch}
    output g2_clk_out,	// G2 bus clock buffer out

    output csn,         // USBN9603 chip select (active low)
    input g2_clk_dly,   // G2 bus system clock 10nsec delay (25MHz)

    inout [5:0] p,      // GPIO port (6 bit)
    output test_out		// test output
);

    parameter BBA_IO_BASE	= 13'h0100;		// BBA I/O base address

    parameter MAGIC_CODE_L	= 16'ha501;		// magic code low word '0xa501'
    parameter MAGIC_CODE_H	= 16'h5a14;		// magic code high word '0x5a14'

    reg [15:0] g2reg;		// for g2 bus tri-state logic
    reg [15:0] sramreg;		// for sram bus tri-state logic
    reg [15:0] bba_do_reg;	// for BBA I/O data out tri-state logic

	wire [31:0] g2_a_node;	// G2 address node
	wire g2_lcs_node;		// G2 lcs node
	wire g2_ucs_node;		// G2 ucs node
	wire g2_dir_node;		// G2 dir node
    wire g2_bus_valid;		// G2 bus valid node
	wire g2_btab_e_node;	// G2 btab_e node
	wire g2_bta_node;		// G2 bta node
	wire g2_btb_node;		// G2 btb node
	wire g2_dcs_node;		// G2 data cycle start pilse node
    wire g2_bus_use;		// G2 bus use flag node
	wire g2_bus_waitn;		// G2 bus wait
	
	wire bba_io_cs;			// BBA I/O base chip selct
	wire ram_port0_cs;		// ram port0 cs (two port RAM)
	wire bba_io_pci_memory_cs;	// BBA I/O in PCI memory CS
	wire bba_io_pci_config_b_cs;// BBA I/O in PCI config B CS (for debug)

	g2_bus g2bus(
	    .clk(g2_clk),			// G2 bus system clock (25MHz)
	    .resetn(g2_resetn),		// G2 bus system reset
	    .aen(g2_aen),			// G2 bus address enable (active low)
	    .lben(g2_lben),			// G2 bus direction and lower byte enable (active low) [change name: dir => g2_lben]
	    .uben(g2_uben),			// G2 bus upper byte enable (active low) [change name: den => g2_uben]
	    .ad(g2_ad),				// G2 bus address/data multiplexed bus (16 bit)

		.a(g2_a_node),			// address bus output
		.lcs(g2_lcs_node),		// lower byte CS (active high)
		.ucs(g2_ucs_node),		// upper byte CS (active high)
		.dir(g2_dir_node),		// direction (high:read low:write)
		.bus_use(g2_bus_use),	// bus use status (active high)
		.bus_waitn(g2_bus_waitn),	// bus wait (active low)
		.bus_valid(g2_bus_valid),	// bus valid status
		.btab_e(g2_btab_e_node),	// BTA BTB enable gate (active high)
	    .bta(g2_bta_node),		// bus termination A (active high)
	    .btb(g2_btb_node),		// bus termination B (active high)
	    .dcs(g2_dcs_node)		// data cycle start pulse
	);

    wire [14:0] s_a_node;	// SRAM address bus
    wire [15:0] s_d_node;	// SRAM data bus
	wire s0_csn_node;		// SRAM 0 chip enable node
    wire s1_csn_node;		// SRAM 1 chip enable node
	wire s0_oen_node;		// SRAM 0 output enable node
    wire s1_oen_node;		// SRAM 1 output enable node
    wire s0_wen_node;		// SRAM 0 write enable node
    wire s1_wen_node;		// SRAM 1 write enable node
	wire s_dir_node;		// SRAM buffer direction node
	wire s_state_node;		// ram state node

	reg	[5:0] pci_config_a_adrs;
	reg [31:0] pci_config_a_data;
	reg [3:0] pci_config_a_be;
	
	reg [7:2] config_b_adrs;
	reg [15:0] reg_work;

	wire [31:0] pci_memory_data = {g2_ad, reg_work};
	
	wire [31:0] pci_m_a;
	wire [31:0] pci_m_di;
	wire [31:0] pci_m_do;
	wire [3:0] pci_m_be;
	
	reg [3:0] pci_memory_be;
	
	wire pci_bus_req;
	reg pci_config_a_cs;
	wire pci_config_b_cs;
	wire pci_memory_cs;
	reg pci_bus_req_reg;
	wire pci_bus_waitn;
	wire pci_bus_end;
	reg bus_end;
	
	reg pci_config_a_rw;
	wire pci_m_rw;
	wire config_a_use;
	
	assign pci_bus_req = (~config_a_use & (pci_memory_cs | pci_config_b_cs)) | (config_a_use & pci_config_a_cs);
	assign pci_m_a = pci_memory_cs ? {g2_a_node[31:2], 2'b00} : {24'h8000_00, pci_config_a_cs ? pci_config_a_adrs : config_b_adrs, 2'b00};
	assign pci_m_di = pci_memory_cs ? pci_memory_data : (pci_config_a_cs ? pci_config_a_data : pci_memory_data);
	assign pci_m_be = pci_memory_cs ? pci_memory_be : (pci_config_a_cs ? pci_config_a_be : pci_memory_be);
	assign pci_m_rw = pci_memory_cs ? ~g2_dir_node : (pci_config_a_cs ? pci_config_a_rw : ~g2_dir_node);
	assign g2_bus_waitn = ~bus_end;
//	assign g2_bus_waitn = (g2_bus_valid & pci_bus_req_reg) ? pci_bus_waitn : 1'b1;
//	assign g2_bus_waitn = (g2_bus_valid & (ram_port0_cs | ((bba_io_pci_memory_cs | bba_io_pci_config_b_cs) & bba_io_cs))) ? pci_bus_waitn : 1'b1;
//	assign g2_bus_waitn = 1'b1;

	wire [31:0] pci_m_ad_do;
	wire [3:0] pci_m_cbe;
	wire pci_reqan_node;
	wire pci_m_framen;
	wire pci_m_irdyn;
	wire pci_m_idsel;
	
	wire pci_m_ad_e;
	wire pci_m_cbe_e;
	wire pci_m_frame_e;
	wire pci_m_irdy_e;
	wire pci_m_parity_e;

	wire [31:0] pci_s_ad_do;
	wire pci_s_trdyn;
	wire pci_s_devseln;
	wire pci_s_stopn;

	wire pci_s_ad_e;
	wire pci_s_trdy_e;
	wire pci_s_devsel_e;
	wire pci_s_parity_e;
	wire pci_s_stop_e;
	wire par_node;
	
	wire pci_gntan_node;
	wire pci_gntbn_node;
	assign pci_gntbn = pci_gntbn_node;
	
	assign pci_perrn = 1'bz;
	assign pci_serrn = 1'bz;
	
	assign pci_ad = pci_m_ad_e ? pci_m_ad_do : (pci_s_ad_e ? pci_s_ad_do : 32'hzzzzzzzz);
	assign pci_cbe = pci_m_cbe_e ? pci_m_cbe : 4'hz;
	assign pci_par = pci_s_parity_e | pci_m_parity_e ? par_node : 1'bz;
	assign pci_framen = pci_m_frame_e ? pci_m_framen : 1'bz;
	assign pci_irdyn = pci_m_irdy_e ? pci_m_irdyn : 1'bz;
	assign pci_trdyn = pci_s_trdy_e ? pci_s_trdyn : 1'bz;
	assign pci_idsel = pci_m_idsel;
	assign pci_devseln = pci_s_devsel_e ? pci_s_devseln : 1'bz;
	assign pci_stopn = pci_s_stop_e ? pci_s_stopn : 1'bz;
	
	pci_master pcimas(
		.clk(g2_clk),				// PCI clock
		.resetn(g2_resetn),			// PCI reset (active low)
		.ad_di(pci_ad),				// PCI ad input bus (32bit)
		.ad_do(pci_m_ad_do),		// PCI ad output bus (32bit)
		.cbe(pci_m_cbe),			// PCI command / byte bit map bus (4bit)
		.reqan(pci_reqan_node),		// PCI bus master req A
		.gntan(pci_gntan_node),		// PCI bus master gnt A
		.framen(pci_m_framen),		// PCI frame (active low)
		.irdyn(pci_m_irdyn),		// PCI irdy (active low)
		.trdyn(pci_trdyn),			// PCI trdy (active low)
		.devseln(pci_devseln),		// PCI devsel (active low)
		.idsel(pci_m_idsel),		// PCI idsel {for RTL8139C} (active high)
		.stopn(pci_stopn),			// PCI stop (active low)
		
		.ad_e(pci_m_ad_e),			// ad enable (active high)
		.cbe_e(pci_m_cbe_e),		// cbe enable (active high)
		.frame_e(pci_m_frame_e),	// frame enable (active high)
		.irdy_e(pci_m_irdy_e),		// irdy enable (active high)
		.parity_e(pci_m_parity_e),	// parity enable (active high)

		.bus_req(pci_bus_req),		// bus request (active high)
		.a(pci_m_a),				// address input (msb(31): config flag)
		.be(pci_m_be),				// bit enable input
		.di(pci_m_di),				// data input
		.do(pci_m_do),				// data output
		.rw(pci_m_rw),				// read(low)/write(high)
//		.bus_waitn(pci_bus_waitn),	// bus wait (active low)
		.bus_end(pci_bus_end)		// bus end pulse (active high)
	);

	pci_slave pcisla(
		.clk(g2_clk),				// PCI clock
		.resetn(g2_resetn),			// PCI reset
		.ad_di(pci_ad),				// PCI ad input bus (32bit)
		.ad_do(pci_s_ad_do),		// PCI ad output bus (32bit)
		.cbe(pci_cbe),				// PCI command / byte bit map bus (4bit)
		.framen(pci_framen),		// PCI frame
		.irdyn(pci_irdyn),			// PCI irdy
		.trdyn(pci_s_trdyn),		// PCI trdy
		.devseln(pci_s_devseln),	// PCI devsel
		.stopn(pci_s_stopn),		// PCI stop
		
		.ad_e(pci_s_ad_e),			// ad enable
		.trdy_e(pci_s_trdy_e),		// trdy enable
		.devsel_e(pci_s_devsel_e),	// devsel enable
		.parity_e(pci_s_parity_e),	// parity enable
		.stop_e(pci_s_stop_e),		// stop enable

//		.stop_req(1'b0),			// stop request {disconnect} (active high)
		.stop_req(~pci_reqan_node),	// stop request {disconnect} (active high)

	    .m_a(s_a_node),			// SRAM address bus (15bit)
	    .m_di(sram_d),			// SRAM data input (16bit)
	    .m_do(s_d_node),		// SRAM data output (16bit)
	    .m0_csn(s0_csn_node),	// SRAM 0 chip select {lower byte} (active low)
	    .m1_csn(s1_csn_node),	// SRAM 1 chip select {upper byte} (active low)
	    .m0_oen(s0_oen_node),	// SRAM 0 output enable {lower byte} (active low)
	    .m1_oen(s1_oen_node),	// SRAM 1 output enable {upper byte} (active low)
	    .m0_wen(s0_wen_node),	// SRAM 0 write enable {lower byte} (active low)
	    .m1_wen(s1_wen_node),	// SRAM 1 write enable {upper byte} (active low)
	    .m_dir(s_dir_node)		// SRAM data bus direction (L:read H:write)
	);

	pci_arbitration pciarb(
		.reqan(pci_reqan_node),	// PCI bus master req A
		.gntan(pci_gntan_node),	// PCI bus master gnt A
		.reqbn(pci_reqbn),		// PCI bus master req B
		.gntbn(pci_gntbn_node),	// PCI bus master gnt B

		.framen(pci_framen),	// PCI frame
		.irdyn(pci_irdyn),		// PCI irdy
		
		.clk(g2_clk),			// PCI clock
		.resetn(g2_resetn)		// PCI reset
	);

	pci_prity pcipar(
		.ad(pci_ad),			// PCI address / data bus (32bit)
		.cbe(pci_cbe),			// PCI command / byte map bus (4bit)
		.parity(par_node),		// PCI parity
		
		.clk(g2_clk),			// PCI clock
		.resetn(g2_resetn),		// PCI reset
		.enable(1'b1)			// ad / cbe enable
	);

	// SRAM assign
    assign sram_a = s_a_node;			// SRAM address bus
    assign sram_d = s_dir_node ? s_d_node : 16'hzzzz;
	assign sram0_oen = s0_oen_node;		// SRAM 0 output enable
    assign sram1_oen = s1_oen_node;		// SRAM 1 output enable
    assign sram0_wen = s0_wen_node;		// SRAM 0 write enable
    assign sram1_wen = s1_wen_node;		// SRAM 1 write enable
//    assign sram0_csn = 1'b0;		// SRAM CS0 fix low
//    assign sram1_csn = 1'b0;		// SRAM CS1 fix low
    assign sram0_csn = s0_csn_node;		// SRAM CS0 fix low
    assign sram1_csn = s1_csn_node;		// SRAM CS1 fix low

	// test output
	assign test_out = pci_m_irdyn;			// 1'b1;
//	assign test_out = pci_bus_req_reg;			// 1'b1;
	
    // GPIO port assign
    assign p[5] = 1'b0;   // P5
    assign p[4] = 1'b0;   // P4
    assign p[3] = 1'b0;   // P3
    assign p[2] = 1'b0;   // P2
    assign p[1] = 1'b0;   // P1
    assign p[0] = 1'b0;   // P0

	// 'g2_irqan' siganl assign
    assign g2_irqan = 1'bz; 	// assign 'g2_irqan'
    assign g2_irqbn = 1'bz;		// assign 'g2_irqbn'

    // G2 bus termination control A/B (for byte access)
    assign g2_btan = g2_btab_e_node ? ~g2_bta_node : 1'bz;
    assign g2_btbn = g2_btab_e_node ? ~g2_btb_node : 1'bz;

	assign bba_io_cs = g2_a_node[28:16] == BBA_IO_BASE;
	assign ram_port0_cs = g2_a_node[28:16] == `DMA_BUFFER;
	assign g2_bus_use = ram_port0_cs | bba_io_cs;
	
	assign bba_io_pci_memory_cs = g2_a_node[15:8] == 8'h17;
	assign bba_io_pci_config_b_cs = (g2_a_node[15:8] == 8'h18) & (g2_a_node[7:2] == 7'b0000_10);

    // G2 bus tri-state buffer logic
    assign g2_ad = g2reg;

    always @(g2_bus_valid or g2_ucs_node or g2_lcs_node or g2_dir_node or ram_port0_cs or bba_io_cs or bba_do_reg or pci_m_do) begin
    	if (g2_bus_valid & g2_dir_node) begin    // read
            if (ram_port0_cs) begin
            	if (g2_a_node[1]) begin
					g2reg[7:0]  <= g2_lcs_node ? pci_m_do[23:16] : 8'hzz;
					g2reg[15:8] <= g2_ucs_node ? pci_m_do[31:24] : 8'hzz;
            	end
            	else begin
					g2reg[7:0]  <= g2_lcs_node ? pci_m_do[7:0]  : 8'hzz;
					g2reg[15:8] <= g2_ucs_node ? pci_m_do[15:8] : 8'hzz;
            	end
            end
            else if (bba_io_cs) begin
				g2reg[7:0]  <= g2_lcs_node ? bba_do_reg[7:0]  : 8'hzz;
				g2reg[15:8] <= g2_ucs_node ? bba_do_reg[15:8] : 8'hzz;
            end
	        else begin
	            g2reg <= 16'hzzzz;
	        end
        end
        else begin
			g2reg <= 16'hzzzz;
		end
    end

	wire [31:0] magic_res_node;
	reg magic_l_valid;	// magic code low word valid flag
	reg magic_valid;	// magic code valid flag
	reg magic_res;		// magic code result flag (RTL8139C configuration end flag)
	reg [31:0] reg_1414;
	reg [31:0] reg_1420;
	reg [31:0] reg_1424;
	reg [31:0] reg_1428;
	reg [31:0] reg_142c;
	reg long_flag;
	reg [3:0] config_state;

	assign magic_res_node = {31'b0000000000000000000000000000000, magic_res};

	// RTL8139C configuration constant define (for MAGIC code sequence)
	parameter CFG_COMMAND_DATA	= 32'hxxxx0006;	// configuration COMMAND data (word)
	parameter CFG_COMMAND_ADRS	= 6'b000001;	// configuration COMMAND address (0x04)
	parameter CFG_COMMAND_BE	= 4'b1100;		// configuration COMMAND byte enable (d[15:0])

//	parameter CFG_LTR_DATA		= 32'hxxxx14xx;	// configuration LTR data {master latency timer} (byte)
	parameter CFG_LTR_DATA		= 32'hxxxx0axx;	// configuration LTR data {master latency timer} (byte)
//	parameter CFG_LTR_DATA		= 32'hxxxx40xx;	// configuration LTR data {master latency timer} (byte)
	parameter CFG_LTR_ADRS		= 6'b000011;	// configuration LTR address (0x0d)
	parameter CFG_LTR_BE		= 4'b1101;		// configuration LTR byte enable (d[15:8])
	
	parameter CFG_MAR_DATA		= 32'h01001700;	// configuration MAR data {memory base address} (long)
	parameter CFG_MAR_ADRS		= 6'b000101;	// configuration MAR address (0x14)
	parameter CFG_MAR_BE		= 4'b0000;		// configuration MAR byte enable (d[31:0])
	
	reg old_magic_valid;
	reg [1:0] cfg_a;
	
	assign config_a_use = ~(config_state == 4'b0000);	// configulation A use flag
	
	// config data
	always @(cfg_a) begin
		case (cfg_a)
			0: pci_config_a_data <= CFG_LTR_DATA;
			1: pci_config_a_data <= CFG_MAR_DATA;
			2: pci_config_a_data <= CFG_COMMAND_DATA;
		endcase
	end
	always @(cfg_a) begin
		case (cfg_a)
			0: pci_config_a_adrs <= CFG_LTR_ADRS;
			1: pci_config_a_adrs <= CFG_MAR_ADRS;
 			2: pci_config_a_adrs <= CFG_COMMAND_ADRS;
		endcase
	end
	always @(cfg_a) begin
		case (cfg_a)
			0: pci_config_a_be <= CFG_LTR_BE;
			1: pci_config_a_be <= CFG_MAR_BE;
			2: pci_config_a_be <= CFG_COMMAND_BE;
		endcase
	end
	
	// MAGIC code state machine (RTL8139C configuration)
	always @(posedge g2_clk or negedge g2_resetn) begin
		if (~g2_resetn) begin
			magic_res <= 1'b0;
			pci_config_a_cs <= 1'b0;	// CS off
			pci_config_a_rw <= 1'b0;	// read
			old_magic_valid <= 1'b0;
			config_state <= 4'b0000;
		end
		else begin
			old_magic_valid <= magic_valid;
			
			if (config_state == 4'b0000) begin
				if (magic_valid & ~old_magic_valid & ~magic_res) begin
					if (~cfg_a_disn) begin
						config_state <= 4'b0111;	// debug: cfg_a_disn low then last state (non configration)
					end
					else begin
						// RTL8139C configuration start
						pci_config_a_rw <= 1'b1;	// write
						config_state <= config_state + 4'b0001;
					end
				end
			end

			else if (config_state == 4'b0001) begin		// config LTR register (master latency timer)
				cfg_a <= 2'd0;	// config address 0
				pci_config_a_cs <= 1'b1;
				config_state <= config_state + 4'b0001;
			end
			else if (config_state == 4'b0010) begin		// wait PCI bus access
				if (pci_bus_end) begin
					pci_config_a_cs <= 1'b0;
					config_state <= config_state + 4'b0001;
				end
			end

			else if (config_state == 4'b0011) begin		// config MAR register (base memory address)
				cfg_a <= 2'd1;	// config address 1
				pci_config_a_cs <= 1'b1;
				config_state <= config_state + 4'b0001;
			end
			else if (config_state == 4'b0100) begin		// wait PCI bus access
				if (pci_bus_end) begin
					pci_config_a_cs <= 1'b0;
					config_state <= config_state + 4'b0001;
				end
			end

			else if (config_state == 4'b0101) begin		// config COMMAND register
				cfg_a <= 2'd2;	// config address 2
				pci_config_a_cs <= 1'b1;
				config_state <= config_state + 4'b0001;
			end
			else if (config_state == 4'b0110) begin		// wait PCI bus access
				if (pci_bus_end) begin
					pci_config_a_cs <= 1'b0;
					config_state <= config_state + 4'b0001;
				end
			end

			else if (config_state == 4'b0111) begin		// last state
				pci_config_a_rw <= 1'b0;	// read
				magic_res <= 1'b1;			// config done.
				config_state <= 4'b0000;
			end
		end
	end

	assign pci_memory_cs = (ram_port0_cs | (bba_io_pci_memory_cs & bba_io_cs)) & pci_bus_req_reg;
	assign pci_config_b_cs = bba_io_pci_config_b_cs & bba_io_cs & pci_bus_req_reg;
	
	// write BBA registers
	always @(posedge g2_clk or negedge g2_resetn) begin
		if (~g2_resetn) begin
			magic_l_valid <= 1'b0;
			magic_valid <= 1'b0;
		end
		else begin
			if (g2_dcs_node & bba_io_cs & ~g2_dir_node) begin
				if (g2_a_node[15:8] == 8'h14) begin
					case (g2_a_node[7:1])
						// 0xa1001414 - 0xa1001417 : ???
						7'h0a:
							begin
								if (g2_lcs_node) reg_1414[7:0]  <= g2_ad[7:0];
								if (g2_ucs_node) reg_1414[15:8] <= g2_ad[15:8];
							end
						7'h0b:
							begin
								if (g2_lcs_node) reg_1414[23:16] <= g2_ad[7:0];
								if (g2_ucs_node) reg_1414[31:24] <= g2_ad[15:8];
							end
						7'h0c,
						7'h0d:	// magic code register
							begin
								if (~magic_res) begin
									if (~magic_l_valid) begin
										if (~g2_aen & ~g2_a_node[1] & (g2_ad == MAGIC_CODE_L)) magic_l_valid <= 1'b1;
									end
									else begin
										if (g2_a_node[1] & (g2_ad == MAGIC_CODE_H)) begin
											magic_valid <= 1'b1;	// magic code valid
										end
										else magic_l_valid <= 1'b0;
									end
								end
							end
						7'h10:
							begin
								if (g2_lcs_node) reg_1420[7:0]  <= g2_ad[7:0];
								if (g2_ucs_node) reg_1420[15:8] <= g2_ad[15:8];
							end
						7'h11:
							begin
								if (g2_lcs_node) reg_1420[23:16] <= g2_ad[7:0];
								if (g2_ucs_node) reg_1420[31:24] <= g2_ad[15:8];
							end
						7'h12:
							begin
								if (g2_lcs_node) reg_1424[7:0]  <= g2_ad[7:0];
								if (g2_ucs_node) reg_1424[15:8] <= g2_ad[15:8];
							end
						7'h13:
							begin
								if (g2_lcs_node) reg_1424[23:16] <= g2_ad[7:0];
								if (g2_ucs_node) reg_1424[31:24] <= g2_ad[15:8];
							end
						7'h14:
							begin
								if (g2_lcs_node) reg_1428[7:0]  <= g2_ad[7:0];
								if (g2_ucs_node) reg_1428[15:8] <= g2_ad[15:8];
							end
						7'h15:
							begin
								if (g2_lcs_node) reg_1428[23:16] <= g2_ad[7:0];
								if (g2_ucs_node) reg_1428[31:24] <= g2_ad[15:8];
							end
						7'h16:
							begin
								if (g2_lcs_node) reg_142c[7:0]  <= g2_ad[7:0];
								if (g2_ucs_node) reg_142c[15:8] <= g2_ad[15:8];
							end
						7'h17:
							begin
								if (g2_lcs_node) reg_142c[23:16] <= g2_ad[7:0];
								if (g2_ucs_node) reg_142c[31:24] <= g2_ad[15:8];
							end
					endcase
				end
				if (g2_a_node[15:8] == 8'h18) begin
					if (g2_a_node[7:1] == 7'b0000_011) begin
						if (g2_lcs_node) config_b_adrs <= g2_ad[7:2];
					end
				end
			end
		end
	end

	// G2 => PCI bus request logic
	//	Write FIFO unused. The access of the G2 bus is converted directly into PCI bus.
	//	G2 bus byte/word/long => PCI bus long (byte enable map) convert
	//	control siganls:
	//		pci_bus_req_reg : PCI master bus request
	//		bus_end : G2 bus wait control
	always @(posedge g2_clk or negedge g2_resetn) begin
		if (~g2_resetn) begin
			pci_bus_req_reg <= 1'b0;
			long_flag <= 1'b0;
			bus_end <= 1'b0;
		end
		else begin
			if (~(g2_bus_valid)) begin
				long_flag <= 1'b0;
				pci_bus_req_reg <= 1'b0;
				bus_end <= 1'b0;
			end
			else begin
				if (pci_bus_req_reg == 1'b0) begin
					if (g2_dcs_node & (ram_port0_cs | ((bba_io_pci_memory_cs | bba_io_pci_config_b_cs) & bba_io_cs))) begin
						if (long_flag == 1'b0) pci_memory_be <= ~g2_aen ? 4'B0000 : (g2_a_node[1] ? {~g2_ucs_node, ~g2_lcs_node, 2'b11} : {2'b11, ~g2_ucs_node, ~g2_lcs_node});
						if (~g2_aen) long_flag <= 1'b1;
						if (g2_dir_node) begin	// read
							if (long_flag == 1'b0) begin
								pci_bus_req_reg <= 1'b1;
								bus_end <= 1'b1;
							end
						end
						else begin				// write
							if (long_flag == 1'b0) begin
								reg_work <= g2_ad;
								if (g2_aen) begin
									pci_bus_req_reg <= 1'b1;
									bus_end <= 1'b1;
								end
							end
							else begin
								pci_bus_req_reg <= 1'b1;
								bus_end <= 1'b1;
							end
						end
					end
				end
				
				if (pci_bus_req_reg == 1'b1) begin
					if (pci_bus_end) bus_end <= 1'b0;
					if (g2_dir_node) begin	// read
						if (g2_bta_node) begin
							if (long_flag) begin
								long_flag <= 1'b0;
							end
							else begin
								pci_bus_req_reg <= 1'b0;
							end
						end
					end
					else begin				// write
						if (g2_bta_node) begin
							long_flag <= 1'b0;
							pci_bus_req_reg <= 1'b0;
						end
					end
				end
			end
		end
	end

	// read BBA registers
	always @(g2_a_node[15:1] or reg_1414 or magic_res_node or magic_res or reg_1420 or reg_1424 or reg_1428 or reg_142c or pci_ad or pci_cbe or config_b_adrs or pci_m_do) begin
		if (g2_a_node[15:8] == 8'h14) begin
			case (g2_a_node[7:1])
				// 0xa1001400 - 0xa100140f : "GAPSPCI_BRIDGE_2" strings
				7'h00: bba_do_reg <= 16'h4147;	// "GA"
				7'h01: bba_do_reg <= 16'h5350;	// "PS"
				7'h02: bba_do_reg <= 16'h4350;	// "PC"
				7'h03: bba_do_reg <= 16'h5f49;	// "I_"
				7'h04: bba_do_reg <= 16'h5242;	// "BR"
				7'h05: bba_do_reg <= 16'h4449;	// "ID"
				7'h06: bba_do_reg <= 16'h4547;	// "GE"
				7'h07: bba_do_reg <= 16'h325f;	// "_2"
				// 0xa1001410 - 0xa1001413 : ???
				7'h08: bba_do_reg <= 16'h3000;	// 0x3000 ???
				7'h09: bba_do_reg <= 16'h0c00;	// 0x0c00 ???
				// 0xa1001414 - 0xa1001417 : ???
				7'h0a: bba_do_reg <= reg_1414[15:0];
				7'h0b: bba_do_reg <= reg_1414[31:16];
				// 0xa1001418 - 0xa100141b : magic code sequence result
				7'h0c: bba_do_reg <= magic_res_node[15:0];
				7'h0d: bba_do_reg <= magic_res_node[31:16];

				// 0xa1001420 - 0xa1001423 : ???
				7'h10: bba_do_reg <= reg_1420[15:0];
				7'h11: bba_do_reg <= reg_1420[31:16];
				// 0xa1001424 - 0xa1001427 : ???
				7'h12: bba_do_reg <= reg_1424[15:0];
				7'h13: bba_do_reg <= reg_1424[31:16];
				// 0xa1001428 - 0xa100142b : ???
				7'h14: bba_do_reg <= reg_1428[15:0];
				7'h15: bba_do_reg <= reg_1428[31:16];
				// 0xa100142c - 0xa100142f : ???
				7'h16: bba_do_reg <= reg_142c[15:0];
				7'h17: bba_do_reg <= reg_142c[31:16];
				default: bba_do_reg <= 16'hxxxx;
			endcase
		end
		else if (g2_a_node[15:8] == 8'h17) begin
			// 0xa1001700 - 0xa10017ff : RTL8139C registers
			bba_do_reg <= g2_a_node[1] ? pci_m_do[31:16] : pci_m_do[15:0];
		end
		// debug: PCI bus debug input port
		else if (g2_a_node[15:8] == 8'h18) begin
			case (g2_a_node[7:1])
				// PCI bus wiring test input port
				// 0xa1001800 - 0xa1001803 : pci_ad[31:0]
				7'h00: bba_do_reg <= pci_ad[15:0];	// PCI ad bus lower 16bit
				7'h01: bba_do_reg <= pci_ad[31:16];	// PCI ad bus upper 16bit
				// 0xa1001804 - 0xa1001805 : pci_cbe[3:0]
				7'h02: bba_do_reg <= {12'b0000_0000_0000, pci_cbe[3:0]};	// PCI cbe bus 4bit
				// 0xa1001806 - 0xa1001807 : config_b_adrs
				7'h03: bba_do_reg <= {8'b0000_0000, config_b_adrs, 2'b00};	// PCI config B address register
				// 0xa1001808 - 0xa100180b : config register
				7'h04: bba_do_reg <= pci_m_do[15:0];	// PCI config register lower 16bit
				7'h05: bba_do_reg <= pci_m_do[31:16];	// PCI config register upper 16bit
				default: bba_do_reg <= 16'hxxxx;
			endcase
		end
		else bba_do_reg <= 16'hxxxx;
	end
	
	// 25MHz * 2 test (50MHz)
    assign csn = g2_clk;
    buf(g2_clk_out, g2_clk ^ g2_clk_dly);
    
endmodule

// end of : bba_clone.v